This invention relates to an error detection circuit and an error detection method for use in an information processing system to detect or check an error which may be present in binary signals.
An information processing system of the type described comprises a processing unit operable in response to binary input signals to carry out predetermined calculation or processing in a digital manner and to produce a result of calculation or processing as a binary output signal. It is necessary to guarantee that each of the binary input and output signals is not erroneous in order to carry out such calculation or processing with a high reliability. For this purpose, an error detection circuit is included in the information processing system and is operable in parallel to the processing unit.
A conventional error detection circuit of the type described checks or detects an error in a manner described by G. G. Landon Jr. et al in "Concurrent Error Detection for Group Look-ahead Binary Adders" (IBM Journal of Research and Development, September 1970, pages 563-573) and by F. F. Sellers, Jr. et al in "Error Detecting Logic for Digital Computers" (McGraw Hill Co., Inc., New York, 1968, pages 41-45 and pages 76-80).
More particularly, the error detection circuit at first processes the binary input signals into residues with respect to a modulus number 3 and thereafter carries out calculation modulo 3 to produce an estimation value which is represented modulo 3 and which may be called a modulo-3 estimation value hereinafter. The calculation itself may be identical with the predetermined calculation of the processing unit Under the circumstances, the modulo-3 estimation value has to be coincident with the binary output signal which is expressed modulo 3 when no error occurs in the binary input and output signals. Otherwise, an error takes place in the binary output signal, as mentioned in the above-referenced books.
In the error detection circuit, error detection may be carried out in connection with both the binary input signals in the above-mentioned manner, because the binary input signal might already accompany an error.
At any rate, it is to be noted that the residues and the modulo-3 estimation value are dealt with in the error detection circuit in the form of a binary code of first and second bits which may be recognized as higher and lower significant bits, respectively. In this event, each of the residues and the modulo-3 estimation value can represent zeroth through second binary codes (0, 0), (0, 1), and (1, 0) which may be called defined codes, respectively. This shows that no consideration is paid about a third binary code (1, 1) which may be called an undefined code. This results in a decrease of an error detection rate and in a difficulty of locating an error, as will presently become clear.
For example, let an error or fault take place such that a certain one of the defined codes is undesirably changed to the undefined code in the error detection circuit. Such an error is not always checked or detected in the error detection circuit. In addition, it is difficult to analyze and locate the error changed from the defined codes to the undefined code because the probability of detecting such errors completely depends on a logical structure of the error detection circuit. This shows that such errors might be detected by some logical structure but is not detected by the other logical structure.
A plurality of error detection circuits might be connected from a first stage to a final one so as to successively carry out calculations modulo 3. In the error detection circuits, no information is transmitted from a preceding one of the stages to the following one even when any error takes place in the preceding stage. Therefore, it is difficult to trace or follow a flow of an erroneous data signal in the error detection circuits. Moreover, each error detection circuit often produces an unspecified output signal in response to the undefined code. Such an unspecified output signal is troublesome to handle in designing a large scale integrated circuit. Theoretically, the error detection circuit (mod 3) may be superseded by an error detection circuit (mod m) wherein m is representative of 2.sup.k -1 where k is an integer greater than unity, although such an error detection circuit (mod m) has not actually been present.